The present invention relates generally to data processing, and in particular to branch prediction circuits and methods and systems using the same.
In deeply pipelined processors, successful dynamic branch prediction is crucial to high speed operation. Consequently, a number of branch prediction mechanisms have been developed. One specific mechanism is the Gshare branch prediction mechanism in which a vector is created which captures the outcome of a fixed number of branches that have been fetched immediately before the current instruction fetch. This vector is typically created by shifting a logic 1 or logic 0 into the last position of a shift register when the outcome of a given branch is determined, with a logic 1 representing a branch taken outcome and a logic 0 representing a branch not taken outcome. The bits of the vector are then bitwise XORed with appropriate bits of the current address. The resulting address is used to index into a branch history table entry which typically is a counter which maintains a value which is used for making the prediction (taken/not taken) for the branch.
In highly pipelined superscalar processors, however, instructions are fetched into the pipeline well in advance of their actual execution. As a result, in a high frequency processor, the vector in a conventional global history (global history vector or GHV) register will be based on branch outcomes which have been determined several cycles before the predicted execution of the current instruction. In other words, outcome data for more temporally proximate branches are not available in the vector at the time the vector is needed to make the current prediction.
Consequently, the need has arisen for circuits and methods for improving branch prediction accuracy. Additionally, the values of the GHV generated by such a xe2x80x9cfast forwardedxe2x80x9d instruction fetch may be subject to loss of synchronization with instruction fetches or other errors which become manifest due to events occurring several processor cycles subsequent to the GHV generation. Examples of such events, which may be referred to as fetch redirection events, include cache misses and branch mispredictions. Thus, there is also a need in the art for circuits and methods for recovering the GHV when a fetch redirection event occurs.
The aforementioned needs are addressed by the present invention. Accordingly, there is provided in a first form, a method of recovering a global history vector. The method includes storing first, second and third global history vectors in respective storage elements. A fetch redirection event, corresponding to one of a predetermined set of redirection event types is detected. In response, a current global history vector is reset to a value derived from a selected global history vector selected from one of said first, second and third storage elements.
There is also provided, in a second form, a data processing system. The system includes a central processing unit (CPU) which itself includes a first storage element, a second storage element and a third storage element. The first, second and third storage elements are, respectively, operable for storing a first global history vector generated in a first cycle of the CPU, operable for storing a second global history vector generated in a first succeeding cycle of the CPU, and operable for storing a third global history vector generated in a second succeeding cycle of the CPU. The CPU also contains first logic operable for detecting a fetch redirection event corresponding to one of a predetermined set of fetch redirection event types, and second logic operable for resetting a current global history vector to a value derived from a selected global history vector. The selected global history vector is selected from one of the first, second and third storage elements in response to detecting the redirection event.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.